Simultaneous Imaging and Energy Harvesting in CMOS Image Sensor Pixel

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  • 1.532 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 4, APRIL 2018 Simultaneous Imaging and Energy Harvesting in CMOS Image Sensor Pixels Sung-Yun Park , Kyuseok Lee, Hyunsoo Song, and Euisik Yoon, Member, IEEE Abstract — We present a prototype CMOS active pixel that is capable of simultaneous imaging and energy harvesting without introducing additional in-plane p-n junctions. The prototype pixel uses a vertical p+/nwell/psub junction that is available in standard CMOS processes. Unlike the conventional CMOS electron-based imaging pixels, where the nwell region is used as a sensing node for image capture, we adopted a hole-based imaging technique, while exploiting the nwell region for energy harvesting at a high fill-factor of >94%. To verify the feasibility, CMOS image sensors are fabricated and characterized. We successfully demonstrated that the energy harvesting can be achieved with a power density of 998 pW/klux/mm2, while capturing images at 74.67 pJ/pixel. The fabricated prototype device has achieved the highest power density among the recent state-of-the-art works and can self-sustain its image capturing operation at 15 fps without external power sources above ∼60 klux of illumination. Index Terms— CMOS image sensor (CIS), energy harvesting imager (EHI), simultaneous imaging and energy harvesting, photovoltaic, photodetection. I. INTRODUCTION R ECENTLY, internet of things (IoT) has emerged as a new technological paradigm that may revolutionize our daily life [1]. Smart sensors, which are essential building blocks for the IoT platforms, can be realized in a small form factor at low-power operation nowadays. However, the requirement for distributed IoT sensor nodes is still stringent, particularly in terms of active power consumption. To address this, several potential energy harvesting methods compatible with the IoT platforms have been actively investigated [2], [3]. CMOS image sensors (CIS) have a high potential to be massively deployed in the IoT sensor nodes for monitoring the environments, identifying objects, and making decisions based upon situation awareness. In fact, CIS can operate at ultra-low power and the energy harvesting capability can be easily added by using inherently built-in photodiodes in the sensor [4]–[8]. However, this has not been fully exploited due to the structural (or functional) overlap in the P-N junction diodes. The photovoltaic (energy harvesting) operation cannot Manuscript received February 7, 2018; revised February 23, 2018; accepted February 27, 2018. Date of publication March 1, 2018; date of current version March 22, 2018. The review of this letter was arranged by Editor J. Moon. (Correspondingauthor:Euisik Yoon.) The authors are with the Department of Electrical Engineering and Computer Science, Center for Wireless Integrated MicroSensing and Systems (WIMS2), The University of Michigan, Ann Arbor, MI 48109 USA (e-mail:esyoon@umich.edu). Color versions of one or more of the figures in this letter are available online athttp://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2018.2811342 be simultaneously realized in the given pixel, while photodetection (imaging) operation is conducted. Most of the energy harvesting imagers (EHIs) reconfigure the mode of pixel operation from imaging to energy harvesting by time multiplexing. This results in prevention of simultaneous imaging and energy harvesting. For example [4], Pwell plays a shared junction between the imaging and energy harvesting devices. As a result, it should be either connected to an external storage node for energy harvesting or connected to a signal reference node (usually, ground) for imaging. In another work [6], Nwell is used as a common node for two modes of operation. The Nwell becomes either an energy harvesting node or a sensing node for capturing images. Another approach in the previous EHIs is to place an additional P-N junction(s) in parallel with the existing imaging diode [9]–[11]. Even though this approach can achieve the simultaneous energy harvesting and imaging, it inevitably results in a low fill factor (FF) in the pixel, utilizing pixel area inefficiently. In this letter, we present and investigate a CMOS image sensor (CIS) pixel which realizes simultaneous operation of imaging and energy harvesting in a high FF of > 90 %. The proposed pixel can either be utilized as a standalone energy harvesting imager thanks to its self-sustainability under day light (> 60 klux) or be one of the energy harvesting cores for large sensor nodes to elongate life time. II. DESIGN AND OPERATION Fig. 1 (a) shows the conventional EHI pixel [4]. In the conventional EHI, Pwell must be connected either to the VEH node for energy harvesting or ground for imaging. Therefore, the simultaneous imaging and energy harvesting cannot be realized. To address this problem, we adopted a hole-based imaging technique by accumulating photo-generated holes in the P+ region as a signal-charge carrier [12], [13], as shown in Fig. 1 (b). This pixel utilizes the two vertically-stacked P-N-P junctions in the standard CMOS process without additional masks. A photodiode (DP1) can collect the photocurrents, while a photovoltaic diode (DP2) harvests energy from photons. Thus, the Nwell does not need to be switched for different modes of operation. It can be connected to the same node for continuous energyharvesting:VEH in Fig. 1 (b), assuming VEH is relatively constant. As shown, the structure of the device in Fig. 1 (b) is easily deduced from the conventional structure in Fig. 1 (a) by simply flipping the polarities of the wells and implants from N to P or vice versa (with removing the deep Nwell (DNW)). Even though the pixel in Fig. 1 (b) can provide the simultaneous imaging and energy harvesting, it inherently has a low FF (∼58%) due to the well-to-well separation (d) between 0741-3106 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.htmlfor more information.
  • 2.PARK et SIMULTANEOUS IMAGING AND ENERGY HARVESTING IN CIS PIXELS 533 Fig. 2. Pixel schematic using the proposed EHI image sensor (a), and column circuit used for image readout (b). Fig. 1. (a) Conventional EHI pixel that accumulates photo-generated electrons, (b) variation of the conventional EHI pixel where photogenerated holes are accumulated for simultaneous imaging and energy harvesting, and (c) proposed pixel structure for simultaneous imaging and energy harvesting with a high fill factor. the in-pixel transistor (MP1) and the imaging diode (DP1), restricted by the given process. Moreover, the reset of DP1 in Fig. 1 (b) requires a NMOS transistor (MN1) inside the pixel because of the negative potential of VEH, which results in further reduction of the FF of this device. A. Proposed Device and Pixel Architecture To resolve the issues, we propose an optimized pixel structure in Fig. 1 (c), where P+/Nwell (DP1) and Nwell/Psub (DP2) are used for the simultaneous imaging and energy harvesting, similar to the pixel in Fig. 1 (b), but all PMOS transistors share the same Nwell by connecting VEH to the Psub. Thanks to the Nwell sharing, this pixel inherently has a high FF (∼ 94 %); thus, its energy harvesting efficiency is greatly enhanced. In addition, since the regulated voltage (VDC) is applied to Nwell, instead of VEH, better quality of images can be obtained. The positive potential (∼0.45 V) in Psub induced by the energy harvesting may be a concern; however, Psub can be electrically isolated in the chip packaging. Outside of the pixel, NMOS transistors can be realized by using a DNW if necessary. The introduction of the DNW for NMOS transistors does not affect the pixel FF since the NMOS transistors are used only for the peripheral circuits. In addition, Psub usually exhibits high resistivity due to its low doping concentration. As an energy harvesting node, it can be a serious shortcoming. To overcome this, the substrate contact is placed in every other pixels. Another concern would be whether the overall photo-collection effi- ciency in the proposed structure may be compromised when compared to a standalone energy harvesting diode or a sole photodetector. We investigated the photo-induced currents by device simulations with the process parameters given in [14]. The thicknesses of 0.1 µm and 1.2 µm were used for P+ and Nwell junction depths, respectively. The doping concentrations of 1019 · cm-3, 1017 · cm-3, and 1015 · cm-3 were chosen for P+, Nwell, and Psub, respectively. In the simulation, the short circuit current (ISC) in DP1 was found to be ∼26 % of the total hole current (DP1 and DP2), and ISC in DP2 occupies rest of the portion. The higher portion of ISC in DP2 may come from the larger depletion width (∼0.6 µm in simulation) than that in the P+/Nwell junction (∼0.05 µm in simulation) as well as its larger geometry embracing the entire Psub. The harvesting diode, DP2, recycles ∼74 % of the photo-generated carriers, otherwise wasted in the conventional imagers. When compared to standalone photovoltaic devices, ∼26 % of the hole current in DP1 can be regarded as a loss. However, the proposed device provides additional functionality of imaging from the photodiode realized by DP1 while simultaneously harvesting energy in DP2 from the incident light. In addition, when compared to the conventional EHI architectures [4], [6], the power density of our device is higher thanks to a higher FF. The proposed pixel in Fig. 1 (c) consists of three in-pixel transistors. Fig. 2 (a) shows the schematics of the pixel. The reset (VRST), dc-potential for the Nwell (VDC), energy harvesting node (VEH), and ground are global nodes. The selection signal (VSEL) is for row selection, and VC1 and VC2 are the column-shared nodes. The switches in Fig. 2 (a) are connected to the ground initially. Once the VEH are developed (> 0.2 ∼ 0.3 V), it is connected to VDC generated by using a charge pump or a boost converter [15], [16]. As mentioned, this pixel has three PMOS transistors for reset, selection, and signal readout, while maximizing the FF for energy harvesting. The allowable signal swing range (VS) of the pixel can be extended to VF + VDC , where VF is the forward conduction voltage ofDP1:∼0.55 V if VDC is applied to the Nwell. In fact, this is another advantage of this pixel over the pixel implemented by using the device in Fig. 1 (b). Because the reset transistor should be implemented by using a NMOS transistor (MN1) for the pixel in Fig. 1 (b), the allowable signal swing range is limited by the forward conduction of the body diode (indicated red diode in Fig. 1 (b)) in the NMOS reset transistor (the body of the NMOS should be tied to the Psub; otherwise, it needs a DNW inside the pixel, and results in further decreasing of the FF).
  • 3.534 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 4, APRIL 2018 TABLE I PERFORMANCE SUMMARY AND COMPARISON WITH RECENT WORKS Fig. 3. VOC and ISC in the proposed device and TP (a), Maximum power generated in the proposed devices and TP (b), for different illumination levels. B. CMOS Image Sensor Design Using the proposed pixel architecture, a CIS chip having 100 × 90 pixels is designed to validate the proof of concept. Each pixel is realized in an area of 5 × 5µm2. Fig. 2 (b) shows the column circuit for image readout. The pair of the sensing (MC1) and selection transistors (MC2) already implemented in the pixels (indicated as Mp1 and Mp2 in Fig. 2 (a)). The readout circuit consists of a CMOS latch (back-to-back inverters), SR-latch, and 8b-counter. For better matching between the input transistors (for instance, MP1 in Fig. 2 (a) and MC1 in Fig. 2 (b)) in the readout circuit, the size of the readout transistors (MC1,2) including dummy transistors are by n (=90) times larger than the pixel where n is the number of pixels in a column. Clock, reset, and selection signals are externally provided. The ramp signal is internally generated, but externally programmable. Fig. 4. Images from a CIS using the proposed pixel at different frames per second. III. EXPERIMENTAL RESULTS The proposed pixels with readout circuits are fabricated in 0.18 µm standard CMOS process with 1P6M. For comparison and validation, the test pattern (TP) CIS using the pixel in Fig. 1 (b) is also fabricated. The TP imager has the exactly same readout circuit. The CIS occupies 660 × 860 µm2. A. Energy Harvesting The energy harvesting performance was measured with LSH-7320 LED Solar Simulator (Oriel Instrument). Fig. 3 (a) shows the measured open circuit voltage (VOC) and ISC of the proposed pixel and the TP pixel as a function of various illumination levels. The VOC of the two are saturated at ∼0.45 V and ISC is proportional to the illumination levels. Fig. 3 (b) plots the maximum harvested power as a function of illumination. In experiment, 0.6 V was applied to VDC in the proposed pixel to make DP2 reverse biased. Thanks to the high fill factor and large junction area by the reverse bias, the proposed pixel can harvest ∼30 µW of power at 120 klux illumination. The power consumption of the fabricated CIS core with 0.6 V supply are also plotted in Fig. 6: 3.9 µW at 7.5 frames per seconds (fps) and 10.08 µW for 15 fps, respectively. The proposed pixel is self-sustainable under the condition when the illumination exceeds 60 klux (sunny daylight), while providing 15 fps images, even assuming 80 % power conversion efficiency in a voltage regulator. Under the normal daylight (20∼30 klux), the device is able to generate images at 7.5 fps. The power density of the fabricated device is measured as 998 pW/klux/mm2, which is the highest number ever reported up to date. Table I summaries the performance and compares with the other recent state-of-the-art works. B. Imaging Fig. 4 shows the captured images from the fabricated prototype CIS in a 100×90 spatial resolution at 7.5 and 15 fps, respectively. In these images, the fixed pattern noise (FPNrms) is suppressed from 9.2 % to 3.8% under dark conditions by delta-reset sampling operation [17]. Nevertheless, column fixed-pattern noise (CFPN) is evident in captured images. This CFPN may result from threshold voltage variations of the input transistors (MC1 in Fig. 2 (b)) in the comparator during analogto-digital conversion. The CFPN can be further suppressed by increasing the size of MC1, which can be easily implemented in the future work. The figure of merit (FoM) of the CIS are 57.78 and 74.67 pJ/pixel at 7.5 and 15 fps, respectively. IV. CONCLUSION We propose a prototype CMOS active pixel architecture capable of simultaneous imaging and energy harvesting by exploiting inherently embedded vertical P+-Nwell-Psub junctions in the standard CMOS process and using holes as a charge-carrier for imaging. The proposed pixel achieved a high FF of ∼94 %. To demonstrate the feasibility, we have fabricated a CIS chip and demonstrated the energy harvesting with a power density of 998 pW/klux/mm2, while generating images with an FOM of 74.67 pJ/pixel. The proposed pixel achieves the highest power harvesting density among the recent state-of-the-art EHIs reported up to date, and is able to sustain 15 fps imaging without external power source when the illumination level exceeds 60 klux.
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