海思半导体工程师曾秋玲——考虑温度效应的统计学EM分析方法在FINFET设计上的应用

2020-02-27 676浏览

1.Thermal-aware SEB Methodology for Finfet design EM signoff 曾秋玲/ 工程师海思半导体 1 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
2.Statistical EM Budgeting(SEB) Introduction  Historically designers have compared interconnect DC average current to a conservative fixed limit as, S = Jdesign / Jmax  So if S <= 1, the “design” is reliable, while any interconnect with S > 1 needs to be redesigned. From the process reliability perspective, EM degradation is inherently statistical. There is always observed a wide dispersion in the times observed for identically sized and stressed segments of interconnect to progress to failure.  When reliability design is designed to mean “achieving a chip-level reliability goal, fixed current density design limits become mathematically arbitrary. Only the total statistical risk to the chip is the meaningful. Then if the EM reliability impact of each segment of interconnect at each stress level can be accounted for, the chip-level EM reliability goal can be budgeted among classes of interconnect or chip design subdivisions to minimize the performance limitations. 2 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
3.SEB Methodology  Statistical EM Budgeting (SEB) is a design-specific EM reliability evaluation method which combines design inputs with EM performance for each interconnect wire to compute a total failure rate for the product. A “pass” is ascertained if the design stay within the failure budget.  SEB gives the designers some flexibility in design without imposing a hard EM limit for the whole product, thus enabling higher performance without compromising reliability. 3 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
4.Failure in Time (FIT) Calculation per Wire FITi = (-10)9 LT * ln 1- ln(SDCn *(LT/MTF))   LT = lifetime eg 5 or 10 years.   = std normal cumulative distribution probability  Sdc = severity ratio of Idc, I/Imax:I-> from design, Imax-> defined in design rule manual.  n = current density exponent (from foundry)  MTF = median time to failure MTF(Tfit)=MTF(Tamb) * exp(Ea/Kb *(1/(Tfit+273)-1/(Tamb+273))) Tamb=Ambient Temperature; Tfit=Tamb+ ∆T from self-heating   = sigma, spread in lifetime distribution (from foundry) 4 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
5.Why SEB q EM challenge on advanced FinFet process q EM is significantly impact on FEOL thermal coupling and self-heating q Very difficult to sign-off EM due to EM limit degraded significantly. q Life Time q EM spec definition in DRM are based on 10Y life time. How about 5Y life time? q Realapplication:5% x Life time 125c + 95% x Life time 85c q From one net to a design q If every net satisfy EM spec, the design have high reliability? NO! For example：Condition:TSMC N10, 10Y life time Sdc（I/Imax)=0.8, fail rate =0.15%(1500PPM). If there are many nets with Sdc more than 0.8, the total fail rate is more high. Usually, SOC fail rate < 0.1% 5 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
6.FIT calculation  Statistical EM Budgeting is a design-specific EM reliability evaluation method which combines design inputs with EM performance for each interconnect wire to compute a total failure rate for the product. A “pass” is ascertained if the design stay within the failure budget. FITtotal ∑i ∑j ∑ kFIT (i,j,k) Sub-divisions classes wires 6 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
7.Thermal-Aware SEB Flow Tech file / LIB / Dev Models DSPF w/ Signal RC LEF/DEF/GDS Foundry SH Input Pre-Thermal Power EM Run Signal EM Run RedHawk Totem P/G wire Irms info Signal wire Irms info Thermal Self-heat calculation including thermal coupling Inst Self-heat Report Wire Self-heat Report Thermal Profile / Back-annotation FIT calculation 7 © 2017 ANSYS, Inc. July 31, 2017 FIT Computation Engine FIT report FIT Map ANSYS UGM 2017
8.Self-heating impact on EM Number of EM violations Max EM violation Total FIT @105C w/o Self-heating 2581 168% 23 @105 w/ Self-heating 2664 197% 416 EM@105 w/o SH 1500 1000 500 0 >100 >110 >120 >130 >140 >150 >160 >170 >180 >190 EM@105 w/ SH 1500 1000 500 0 >100 >110 >120 >130 >140 >150 >160 >170 >180 >190 8 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
9.Self-heatingResult:instance delta T Instance Delta T Map The max delta T is 11.8C 9 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017
12.EM sign-off by thermal-aware SEB  Designer should fix 2664 EM violations by traditional EM sign-off method.  Now design can be sign-off if fix less than 200 violations. 0 50 100 150 200 ALL Total FIT of Top FIT wire/via 50 100 150 200 250 300 350 400 450 336.1 394.5 406.7 410.8 416 12 © 2017 ANSYS, Inc. July 31, 2017 ANSYS UGM 2017