def run(self, edit, args):
settings = self.view.settings()
minfo = args['minfo']
params = args['pv']
# retrieve connection
(decl,ac,wc) = self.get_connect(self.view,settings,minfo)
# print('decl = {}\nAC = {}\nwc = {}'.format(decl,ac,wc))
# Instance name
inst = '\t' + settings.get('vhdl.instance_prefix','') + minfo['name'] + settings.get('vhdl.instance_suffix','')
inst += ' : entity work.{}\n'.format(minfo['name'])
# Generic Map
if params :
inst += '\t\tgeneric map (\n'
max_len_l = max([len(x['name']) for x in params])
max_len_r = max([len(x['value']) for x in params])
for i,param in enumerate(params) :
inst += '\t\t\t{} => {}'.format(param['name'].ljust(max_len_l),param['value'].ljust(max_len_r))
if i<len(params)-1:
inst +=','
inst += '\n'
inst += '\t\t)\n'
# Port Map
if minfo['port'] :
inst += '\t\tport map (\n'
max_len_l = max([len(x['name']) for x in minfo['port']])
max_len_r = 0 if not ac else max([len(x) for x in ac])
for i,port in enumerate(minfo['port']) :
inst += '\t\t\t{} => {}'.format(port['name'].ljust(max_len_l), '' if port['name'] not in ac else ac[port['name']].ljust(max_len_r))
# Remove entry of ac if it is the same as the port (to be used by the final report)
if port['name'] in ac and ac[port['name']] == port['name']:
ac.pop(port['name'],0)
if i<len(minfo['port'])-1:
inst +=','
inst += '\n'
inst += '\t\t);\n\n'
report = ''
# Insert code for module Instantiation
self.view.insert(edit, self.view.line(self.view.sel()[0]).a, inst)
# Insert signal declaration if any
if decl:
r_start = self.view.find(r'(?si)^\s*architecture\s+\w+\s+of\s+\w+\s+is(.*?)$',0, sublime.IGNORECASE)
if r_start:
# find position of last ;
r_end = self.view.find(r'(?si);[^;]+begin',0, sublime.IGNORECASE)
if r_end :
# TODO check if not inside a comment ...
r_start.a = r_end.a+1
self.view.insert(edit, r_start.a, '\n'+decl)
report += 'Declaring {} signals\n'.format(len(decl.splitlines()))
else :
report += 'Unable to find declaration region:\n' + decl
if len(ac)>0 :
report+= 'Non-perfect name match for {} port(s) : {}\n'.format(len(ac),ac)
if len(wc)>0 :
report+= 'Found {} mismatch(es) for port(s): {}\n'.format(len(wc),[x for x in wc.keys()])
if report:
sublime_util.print_to_panel(report,'SmartVHDL')
# Find connection between instance port and local signal/port
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