def test():
# We'll add no project file, so the only sources that should
# be fond are VUnit's files
it.assertIn('vunit', sys.modules)
project_filename = p.join(TEST_CONFIG_PARSER_SUPPORT_PATH,
'builder_only_project.prj')
with mock.patch('hdlcc.builders.MSim.file_types',
new_callable=mock.PropertyMock,
return_value=('vhdl', )):
parser = ConfigParser(project_filename)
sources = parser.getSources()
vunit_files = 0
for source in sources:
if 'vunit' in source.filename.lower():
vunit_files += 1
it.assertEqual(len(sources), vunit_files,
"We should only find VUnit files")
# Check that we find no verilog or systemverilog files
for filetype in ('verilog', 'systemverilog'):
it.assertNotIn(filetype, [x.filetype for x in sources],
"We should only find VUnit VHDL files")
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