Verilog2001Parser.java 文件源码

public final PortContext port() throws RecognitionException {
    PortContext _localctx = new PortContext(_ctx, getState());
    enterRule(_localctx, 32, RULE_port);
    int _la;
    try {
        setState(811);
        switch (_input.LA(1)) {
        case T__16:
        case T__17:
        case T__18:
        case Escaped_identifier:
        case Simple_identifier:
            enterOuterAlt(_localctx, 1);
            {
            setState(801);
            _la = _input.LA(1);
            if (_la==T__18 || _la==Escaped_identifier || _la==Simple_identifier) {
                {
                setState(800);
                port_expression();
                }
            }

            }
            break;
        case T__4:
            enterOuterAlt(_localctx, 2);
            {
            setState(803);
            match(T__4);
            setState(804);
            port_identifier();
            setState(805);
            match(T__15);
            setState(807);
            _la = _input.LA(1);
            if (_la==T__18 || _la==Escaped_identifier || _la==Simple_identifier) {
                {
                setState(806);
                port_expression();
                }
            }

            setState(809);
            match(T__17);
            }
            break;
        default:
            throw new NoViableAltException(this);
        }
    }
    catch (RecognitionException re) {
        _localctx.exception = re;
        _errHandler.reportError(this, re);
        _errHandler.recover(this, re);
    }
    finally {
        exitRule();
    }
    return _localctx;
}